1. Field of the Invention
The invention relates generally to an improved write line charge protection circuit for use in memory devices and the method for manufacturing the write line charge protection circuit.
2. Related Art
Flash and other types of electronic memory devices are constructed of memory cells that individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words that may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells, where the data can then be retrieved in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual memory cells typically comprise a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device in which a binary piece of information may be retained. The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be removed or stored in the memory cell. In a read operation, appropriate voltages are applied to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
Flash memory is a non-volatile type of memory that can be rewritten and hold its content without power. Conventional flash memories are constructed in a cell structure, wherein a single bit of information is stored in each flash memory cell. Each flash memory cell includes a transistor structure having a source, a drain, and a channel in a substrate or, as well as a stacked gate structure overlying the channel. The stacked gate may include a gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the p-type conductivity, for example, disposed in the substrate as commonly known by a person having ordinary skill in the art. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator, such as an oxide-nitride-oxide (ONO) layer, having two oxide layers sandwiching a nitride layer. Lastly, a doped polysilicon control gate overlies the interpoly dielectric layer.
Flash memory cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation. The flash memory cells, whether single bit or multiple-bit, may be interconnected in a variety of different configurations. For instance, cells may be configured in a NOR configuration, with the control gates of the cells in a row individually connected to a wordline and the drains of the cells in a particular column connected together by a conductive bitline, in such an arrangement, all the flash cells in the array have their source terminals coupled to a common source terminal, such as Vss or ground. In operation, individual flash cells in such a NOR configuration are addressed via the respective bitline and wordline using peripheral decoder and control circuitry for programming (writing), reading, erasing, or other functions.
Another cell configuration is known as a virtual ground architecture, in which the control gates of the core cells in a row are tied to a common wordline. A typical virtual ground architecture comprises rows of flash memory core cell pairs with a drain of one cell transistor coupled to an associated bitline and to the source of the adjacent core cell transistor. An individual flash cell is selected via the wordline and a pair of bitlines bounding the associated cell. A cell may be read by applying voltages to the control gate (e.g., via the common wordline) and to a bitline coupled to the drain, while the source is coupled to ground (Vss) via another bitline. A virtual ground is thus formed by selectively grounding the bitline associated with the source of the cells that are to be read. Where the core cells are of a dual-bit type, the above connections can be used to read a first bit of the cell, whereas the other bit may be similarly read by grounding the bitline connected to the drain, and applying a voltage to the source terminal via the other bitline.
In the course of manufacturing flash memory devices, certain processing steps involve the use of electrically charged plasma. For instance, ion implantation, plasma etching, plasma enhanced deposition processes and other charged processing operations may damage semiconductor wafers, and the flash memory cells therein. The plasma in such processes includes charged particles, some of which may accumulate on the wafer surface through antenna charging. For example, in back-end interconnect processing, inter layer dielectric (ILD) material is often deposited using plasma enhanced chemical vapor deposition (PECVD) and etched using plasma based reactive ion etching (RIE). In flash memory arrays, the conductive control gate structures are commonly formed as lines of doped polysilicon disposed along rows of cells, which operate as wordlines to selectively access the rows of data stored therein. The polysilicon control gates or wordlines operate as antennas with respect to process-related charging, including process steps involving plasma. If unprotected, the wordline structures accumulate charge and acquire a voltage potential with respect to the wafer substrate, which can discharge through the stacked gate or charge trapping layer, leading to preprogramming or damage of the cells.
Even after the doped polysilicon wordlines are covered with ILD material, process-related charging may cause cell damage. For instance, during back-end interconnect (e.g., metalization) processing, one or more patterned metal layers are formed over and between ILD layers, some of which are connected to the wordlines in the flash array. These metal wordline routing structures may themselves be directly exposed to back-end processes, and operate as charge gathering antennas, where charge accumulating on exposed wordline connections can discharge through the flash memory cells, again leading to damage and/or performance degradation. Wordline protection apparatus and methods are desirable for the manufacture of flash memory devices to inhibit the adverse effects of process-related charging. One example of such a wordline protection structure is fully explained in U.S. Pat. No. 7,160,773, which is incorporated herein by reference in its entirety.
Flash memory is typically tested to determine whether any of the wordlines suffer from current leakage. Accurately determining the amount of current leakage is important because it allows a determination to be made about whether a particular memory cell or sector is functioning properly. Inaccurate current leakage measurements can result in either properly-functioning memory being rejected or in faulty memory being passed. It has been determined that, under certain situations, prior art memory with certain wordline protection structures result in inaccurate measurements of current leakage. Accordingly, improvements are needed to provide memory that allows for accurate measurements of current leakage.